MMC2107 - Freescale Semiconductor

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Timer Modules (TIM1 and TIM2) Freescale Semiconductor, Inc. 15.4 Block Diagram CLK[1:0] SYSTEM CLOCK PR[2:0] PRESCALER PACLK PACLK/256 PACLK/65536 MUX CHANNEL 3 OUTPUT COMPARE TCRE nc... Freescale Semiconductor, I PAOVF TIMCNTH:TIMCNTL 16-BIT COUNTER CHANNEL 0 16-BIT COMPARATOR TIMC0H:TIMC0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TIMC1H:TIMC1L 16-BIT LATCH CHANNEL 2 CHANNEL3 16-BIT COMPARATOR TIMC3H:TIMC3L 16-BIT LATCH TE TIMPACNTH:TIMPACNTL CLEAR COUNTER C0F EDG0A EDG0B C1F EDG1A EDG1B C3F EDG3A EDG3B EDGE DETECT EDGE DETECT EDGE DETECT CxI CxF TOF TOI IOS0 OM:OL0 TOV0 IOS1 OM:OL1 TOV1 IOS3 OM:OL3 TOV3 PEDGE PAE INTERRUPT LOGIC PT0 LOGIC PT1 LOGIC PT3 LOGIC EDGE DETECT INTERRUPT REQUEST CH. 0 CAPTURE CH. 0 COMPARE CH. 1 CAPTURE CH. 1 COMPARE CH.3 CAPTURE PA INPUT CH. 3 COMPARE ICOC0 PIN ICOC1 PIN ICOC3 PIN PACLK/65536 16-BIT COUNTER MUX PAIF PACLK/256 PACLK DIVIDE-BY-64 MODULE CLOCK INTERRUPT REQUEST INTERRUPT LOGIC PAMOD PAOVI PAOVF PAI PAIF Figure 15-1. Timer Block Diagram Technical Data MMC2107 – Rev. 2.0 296 Timer Modules (TIM1 and TIM2) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Timer Modules (TIM1 and TIM2) Modes of Operation 15.5 Modes of Operation This subsection describes the supervisor and user modes, the five low-power options, and test mode. 15.5.1 Supervisor and User Modes nc... Freescale Semiconductor, I 15.5.2 Run Mode 15.5.3 Stop Mode 15.5.4 Wait, Doze, and Debug Modes The SO bit in the chip-select control register determines whether the processor is operating in user mode or supervisor mode. Accessing supervisor address locations while not in supervisor mode causes the timer to assert a transfer error. Clearing the TIMEN bit in the timer system control register 1 (TIMSCR1) or the PAE bit in the pulse accumulator control register (TIMPACTL) reduces power consumption in run mode. Timer registers are still accessible, but all timer functions are disabled. If the central processor unit (CPU) enters stop mode, timer operation stops. Upon exiting stop mode, the timer resumes operation unless stop mode was exited by reset. The timer is unaffected by these low-power modes. 15.5.5 Test Mode A high signal on the TEST pin puts the processor in test mode or special mode. The timer behaves as in user mode, except that timer test registers are accessible. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Timer Modules (TIM1 and TIM2) 297 For More Information On This Product, Go to: www.freescale.com
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