MMC2107 - Freescale Semiconductor

Watchdog Timer Module
Freescale Semiconductor, Inc.
13.6 Memory Map and Registers
This subsection describes the memory map and registers for the
watchdog timer. The watchdog timer has a base address of
0x00c7_0000.
13.6.1 Memory Map
Refer to Table 13-1 for an overview of the watchdog memory map.
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Freescale Semiconductor, I
13.6.2 Registers
Table 13-1. Watchdog Timer Module Memory Map
Address Bits 15–8 Bits 7–0 Access (1)
0x00c7_0000 Watchdog control register (WCR) S
0x00c7_0002 Watchdog modulus register (WMR) S
0x00c7_0004 Watchdog count register (WCNTR) S/U
0x00c7_0006 Watchdog service register (WSR) S/U
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User
mode accesses to supervisor only addresses have no effect and result in a cycle
termination transfer error.
The watchdog timer programming model consists of these registers:
• The watchdog control register (WCR) configures watchdog timer
operation.
• The watchdog modulus register (WMR) determines the timer
modulus reload value.
• The watchdog count register (WCNTR) provides visibility to the
watchdog counter value.
• The watchdog service register (WSR) requires a service
sequence to prevent reset.
Technical Data MMC2107 – Rev. 2.0
274 Watchdog Timer Module MOTOROLA
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