MMC2107 - Freescale Semiconductor

Serial Peripheral Interface Module (SPI)
Freescale Semiconductor, Inc.
is high, the MISO pin is in a high impedance state, and the slave ignores
the SCK input.
NOTE:
When using peripherals with full-duplex capability, do not simultaneously
enable two receivers that drive the same MISO output line.
As long as only one slave drives the master input line, it is possible for
several slaves to receive the same transmission simultaneously.
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Freescale Semiconductor, I
17.8.3 Transmission Formats
17.8.3.1 Transfer Format When CPHA = 1
If the CPHA bit in SPICR1 is clear, odd-numbered edges on the SCK
input latch the data on the MOSI pin. Even-numbered edges shift the
data into the LSB position of the SPI shift register and shift the MSB out
to the MISO pin.
If the CPHA bit is set, even-numbered edges on the SCK input latch the
data on the MOSI pin. Odd-numbered edges shift the data into the LSB
position of the SPI shift register and shift the MSB out to the MISO pin.
The transmission is complete after the eighth shift. The received data
transfers to SPIDR, setting the SPIF flag in SPISR.
The CPHA and CPOL bits in SPICR1 select one of four combinations of
serial clock phase and polarity. Clock phase and polarity must be
identical for the master SPI device and the communicating slave device.
Some peripherals require the first SCK edge to occur before the slave
MSB becomes available at its MISO pin. When the CPHA bit is set, the
master SPI waits for a synchronization delay of one-half SCK clock
cycle. Then it issues the first SCK edge at the beginning of the
transmission. The first edge causes the slave to transmit its MSB to the
MISO pin of the master. The second edge and the following
even-numbered edges latch the data. The third edge and the following
odd-numbered edges shift the latched slave data into the master shift
register and shift master data out on the master MOSI pin.
Technical Data MMC2107 – Rev. 2.0
388 Serial Peripheral Interface Module (SPI) MOTOROLA
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