MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address Register Name Bit Number
Bit 15 14 13 12 11 10 9 Bit 8
0x00c2_0006
0x00c2_0007
Chip Select Control
Register 3 (CSCR3)
See page 527.
Read:
Write:
SO RO PS WWS WE WS2 WS1 WS0
Reset: 0 0 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0
Write:
TAEN
CSEN
Reset: 0 0 0 0 0 0 1 0
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Freescale Semiconductor, I
0x00c2_0008
↓
0x00c2_ffff
Clocks (CLOCK)
0x00c3_0000
0x00c3_0001
0x00c3_0002
Unimplemented
Synthesizer Control
Register (SYNCR)
See page 227.
Synthesizer Status
Register (SYNSR)
See page 230.
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Access results in a bus monitor timeout generating an access termination transfer error.
Bit 15 14 13 12 11 10 9 Bit 8
LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0
Reset: 0 0 1 0 0 0 0 1
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPD0 RSVD1 RSVD0
Reset: 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 Bit 0
Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0
Write:
Reset: Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0
Notes:
1. Reset state determined during reset configuration
2. See the LOCKS and LOCK bit descriptions.
P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 10 of 34)
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA System Memory Map 63
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