MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
Microarchitecture Summary
6.4 Microarchitecture Summary
Figure 6-1 is a block diagram of the M•CORE processor.
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
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The execution unit consists of a 32-bit arithmetic/logic unit, a 32-bit
barrel shifter, a find-first-one unit, result feed-forward hardware, and
miscellaneous support hardware for multiplication, division, and
multiple-register loads and stores.
Freescale Semiconductor, I
DATA CALCULATION
GENERAL-PURPOSE
REGISTER FILE
32 BITS X 16
X PORT
SIGN EXT.
MUX
ALTERNATE
REGISTER FILE
32 BITS X 16
BARREL SHIFTER
MULTIPLIER
DIVIDER
Y PORT
CONTROL
REGISTER FILE
32 BITS X 13
MUX
SCALE
IMMEDIATE
MUX
ADDRESS GENERATION
PC
INCREMENT
ADDRESS MUX
BRANCH
ADDER
INSTRUCTION PIPELINE
ADDRESS
BUS
ADDER/LOGICAL PRIORITY ENCODER/
ZERO DETECT RESULT MUX
INSTRUCTION DECODE
WRITEBACK BUS
H/W ACCELERATOR INTERFACE BUS
DATA
BUS
Figure 6-1. M•CORE Processor Block Diagram
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA M•CORE M210 Central Processor Unit (CPU) 145
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