MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Clock Module
Functional Description
10.8 Functional Description
This subsection provides a functional description of the clock module.
10.8.1 System Clock Modes
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CAUTION:
The system clock source is determined during reset. The value of
V DDSYN is latched during reset and is expected to remain at that state
after reset is negated. If V DDSYN is changed during a reset other than
power-on reset, the internal clocks may glitch as the clock source is
changed between external clock mode and PLL clock mode. Whenever
V DDSYN is changed in reset, an immediate loss of lock condition occurs.
Table 10-6 shows the clock-out frequency to clock-in frequency
relationships for the possible clock modes.
Table 10-6. Clock-Out and Clock-In Relationships
Normal PLL clock mode
Clock Mode PLL Options (1)
1:1 PLL clock mode f sys = f ref
External clock mode f sys = f ref /2
1. f ref = input reference frequency
f sys = CLKOUT frequency
MFD ranges from 0 to 7.
RFD ranges from 0 to 7.
f sys = f ref × (MFD + 2)/2 RFD
XTAL must be tied low in external clock mode when reset is asserted. If
it is not, clocks could be suspended indefinitely.
The external clock is divided by two internally to produce the system
clocks.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Clock Module 235
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