MMC2107 - Freescale Semiconductor

Non-Volatile Memory FLASH (CMFR)
Freescale Semiconductor, Inc.
At this point the CMFR is ready to receive the programming writes, the
erase interlock write, or a write to CMFRMCR for programming the
reset values of the DIS bit, or a write to CMFRRC.
NOTE:
The erase interlock write is a write to any CMFR array location after SES
is set and ERASE = 1.
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Freescale Semiconductor, I
If the ERASE bit is a 0, the CMFR BIU accepts programming writes to
the CMFR array address for programming. The first programming
write selects the program page offset address to be programmed
along with the data for the programming buffers at the location written.
All programming writes after the first write update the program buffers
using the lower address and the block address to select the program
page buffers to receive the data. See 9.7.2.2 Program Page Buffers
for further information. After the data has been written to the program
buffers the EHV bit is set (written to a 1) to start the programming
pulse and lock out further programming writes.
If the ERASE bit is a 1, the CMFR BIU accepts writes to the CMFR
array address for erase. An erase interlock write is required before the
EHV bit can be set.
At the end of the program or erase operation, the SES bit must be
cleared (written to a 0) to return to normal operation and release the
program buffers and the locked bits. The CMFR requires a recovery
time of 16 clocks after negating SES. This means that if a read access
to the CMFR array is done immediately after writing SES = 0, the
access is completed after 16 clocks. Also, the FSTOP bit should not
be asserted during this recovery time.
The default reset state of SES is not configured for program or erase
operation (SES = 0).
EHV — Enable High-Voltage Bit
The read-always EHV bit controls the application of the program or
erase voltage to the CMFR. High-voltage operations to the array,
special shadow locations or NVM registers can occur only if EHV = 1.
EHV can be asserted only after the SES bit has been asserted and a
valid programming write(s) or erase hardware interlock write has
occurred. Attempts to assert EHV when SES is negated (including the
cycle which writes 0 to SES), or when a valid programming write or
erase hardware interlock write has not occurred since SES was
asserted have no effect.
Technical Data MMC2107 – Rev. 2.0
202 Non-Volatile Memory FLASH (CMFR) MOTOROLA
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