MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Memory Map and Registers
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Freescale Semiconductor, I
NOTE:
NOTE:
MSTR — Master Bit
The MSTR bit selects SPI master mode or SPI slave mode operation.
Reset clears MSTR.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
The CPOL bit selects an inverted or non-inverted SPI clock. To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears CPOL.
1 = Active-low clock; SCK idles high
0 = Active-high clock; SCK idles low
CPHA — Clock Phase Bit
The CPHA bit delays the first edge of the SCK clock. Reset sets
CPHA.
1 = First SCK edge at start of transmission
0 = First SCK edge 1/2 cycle after start of transmission
SSOE — Slave Select Output Enable Bit
The SSOE bit and the DDRSP3 bit configure the SS pin as a
general-purpose input or a slave-select output. Reset clears SSOE.
Table 17-3. SS Pin I/O Configurations
DDRSP3 SSOE Master Mode Slave Mode
0 0 Mode-fault input Slave-select input
0 1 General-purpose input Slave-select input
1 0 General-purpose output Slave-select input
1 1 Slave-select output Slave-select input
Setting the SSOE bit disables the mode fault detect function.
LSBFE — LSB-First Enable Bit
The LSBFE enables data to be transmitted LSB first. Reset clears
LSBFE.
1 = Data transmitted LSB first.
0 = Data transmitted MSB first
In SPIDR, the MSB is always bit 7 regardless of the LSBFE bit.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Peripheral Interface Module (SPI) 377
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