MMC2107 - Freescale Semiconductor

Reset Controller Module
Freescale Semiconductor, Inc.
5.7.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as
loss of clock (1) or loss of lock (2), the reset control logic asserts
RSTOUT (4). The reset control logic waits for the PLL to attain lock
(9, 9A) before waiting 512 CLKOUT cycles (10). Then the reset control
logic may latch the configuration according to the RCON pin level (11,
11A) before negating RSTOUT (12).
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Freescale Semiconductor, I
5.7.2.3 Power-On Reset
5.7.3 Concurrent Resets
5.7.3.1 Reset Flow
If a loss of lock occurs during the 512 count (10), the reset flow switches
to (9A) and waits for the PLL to lock before continuing.
When the reset sequence is initiated by power-on reset (0), the same
reset sequence is followed as for the other asynchronous reset sources.
This subsection describes the concurrent resets.
If a power-on reset condition is detected during any reset sequence, the
power-on reset sequence starts immediately (0).
If the external RESET pin is asserted for at least four rising CLKOUT
edges while waiting for PLL lock or the 512 cycles, the external reset is
recognized. Reset processing switches to wait for the external RESET
pin to negate (8).
If a loss of clock or loss of lock condition is detected while waiting for the
current bus cycle to complete (5, 6) for an external reset request, the
cycle is terminated. The reset status bits are latched (7) and reset
processing waits for the external RESET pin to negate (8).
If a loss of clock or loss of lock condition is detected during the 512-cycle
wait, the reset sequence continues after a PLL lock (9, 9A).
Technical Data MMC2107 – Rev. 2.0
140 Reset Controller Module MOTOROLA
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