MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Top-Level Test Access Port (TAP)
21.3 Top-Level Test Access Port (TAP)
The MMC2107 provides a dedicated user-accessible test access port
(TAP) that is fully compatible with the IEEE 1149.1 Standard Test
Access Port and Boundary-Scan Architecture. Problems associated with
testing high-density circuit boards have led to development of this
proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The
MMC2107 implementation supports circuit-board test strategies based
on this standard.
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Freescale Semiconductor, I
CAUTION:
The top-level TAP consists of five dedicated signal pins, a 16-state TAP
controller, an instruction register, and three data registers, a boundary
scan register for monitoring and controlling the device’s external pins, a
device identification register, and a 1-bit bypass (do nothing) register.
The top-level TAP provides the ability to:
1. Perform boundary scan (external pin) drive and monitor
operations to test circuitry external to the MMC2107
2. Disable the MMC2107’s output pins
3. Read the MMC2107’s IDCODE device identification register
Certain precautions must be observed to ensure that the top-level
TAP module does not interfere with non-test operation. See
21.10 Non-Scan Chain Operation for details.
The MMC2107’s top-level TAP module includes a TAP controller, a 4-bit
instruction register, and three test data registers (a 1-bit bypass register,
a 200-bit boundary scan register, and a 32-bit IDCODE register). The
top-level tap controller and the low-level (OnCE) TAP controller share
the external signals described here.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 537
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