MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Introduction
21.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . .577
21.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . .579
21.14.12.5 Processor Status Register . . . . . . . . . . . . . . . . . . . . . .579
21.14.13 Instruction Address FIFO Buffer (PC FIFO) . . . . . . . . . . .580
21.14.14 Reserved Test Control Registers . . . . . . . . . . . . . . . . . . .581
21.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
21.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
21.14.17 Target Site Debug System Requirements . . . . . . . . . . . .582
21.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . .582
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Freescale Semiconductor, I
21.2 Introduction
The MMC2107 has two JTAG (Joint Test Action Group) TAP (test
access port) controllers:
1. A top-level controller that allows access to the MMC2107’s
boundary scan (external pins) register, IDCODE register, and
bypass register
2. A low-level OnCE (on-chip emulation) controller that allows
access to MMC2107’s central processor unit (CPU) and
debugger-related registers
At power-up, only the top-level TAP controller will be visible. If desired,
a user can then enable the low-level OnCE controller which will in turn
disable the top-level TAP controller. The top-level TAP controller will
remain disabled until either power is removed and reapplied to the
MMC2107 or until the test reset signal, TRST, is asserted (logic 0).
The OnCE TAP controller can be enabled in either of two ways:
1. With the top-level TAP controller in its test-logic-reset state:
a. Deassert TRST, test reset (logic1)
b. Assert DE, the debug event (logic 0) for two TCLK, test clock,
cycles
2. Shift the ENABLE_MCU_ONCE instruction, 0x3, into the top-level
TAP controller’s instruction register (IR) and pass through the TAP
controller state update-IR.
Refer to Figure 21-1.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 535
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