MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
Functional Description
T3
S2
S3
T1 T2 T6
T4
RESET
S1
T7
S4
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Freescale Semiconductor, I
State
S1
S2
Figure 9-10. Erase State Diagram
Table 9-10 Erase Interlock State Descriptions
Mode
Normal operation: Normal array reads and
register accesses. Block protect information
and pulse-width timing control can be
modified.
Erase hardware interlock write: Normal read
operation. CMFR accepts erase hardware
interlock write to any array location. Normal
register access (except CMFRMCR).
CMFRCTL write cannot set EHV. Register
write (except CMFRMCR) is not erase
hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3.
T9
Next
State
T8
S5
T5
Transition Requirement
S2 T2 Write ERASE = 1 and SES = 1
S1
S3
T1 Write SES = 0 or a master reset
T3
Hardware interlock: Write to any array
location is erase interlock write. Register
write other than CMFRMCR is not erase
hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3; NVM fuses cleared during high-voltage
pulse
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Non-Volatile Memory FLASH (CMFR) 217
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