MMC2107 - Freescale Semiconductor

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System Memory Map Freescale Semiconductor, Inc. Address Register Name Bit Number Bit 7 6 5 4 3 2 1 Bit 0 0x00cc_0006 0x00cd_0006 SCI Data Register High (SCIDRH) See page 345. Read: Write: R8 T8 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0x00cc_0007 0x00cd_0007 SCI Data Register Low (SCIDRL) See page 345. Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I 0x00cc_0008 0x00cd_0008 0x00cc_0009 0x00cd_0009 0x00cc_000a 0x00cd_000a 0x00cc_000b ↓ 0x00cc_000f 0x00cd_000b ↓ 0x00cd_000f SCI Pullup and Reduced Drive Register (SCIPURD) See page 346. SCI Port Data Register (SCIPORT) See page 347. SCI Data Direction Register (SCIDDR) See page 348. Reserved Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 SCISDOZ 0 RSVD5 RDPSCI 0 0 RSVD1 Reset: 0 0 0 0 0 0 0 0 Read: Write: PUPSCI Bit 7 6 5 4 3 2 1 Bit 0 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0 Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDRSC1 DDRSC0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit 7 6 5 4 3 2 1 Bit 0 0x00cc_0010 ↓ 0x00cc_ffff 0x00cd_0010 ↓ 0x00cd_ffff Unimplemented Access results in a bus monitor timeout generating an access termination transfer error. P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception. Figure 2-2. Register Summary (Sheet 27 of 34) Technical Data MMC2107 – Rev. 2.0 80 System Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. System Memory Map Register Map Address Register Name Bit Number Timer 1 (TIM1) and Timer 2 (TIM2) Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####. Bit 7 6 5 4 3 2 1 Bit 0 0x00ce_0000 0x00cf_0000 Timer Input Capture/ Output Compare Select Register (TIMIOS) See page 300. Read: 0 0 0 0 IOS3 IOS2 IOS1 IOS0 Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 nc... 0x00ce_0001 0x00cf_0001 Timer Compare Force Register (TIMCFORC) See page 301. Read: 0 0 0 0 0 0 0 0 Write: FOC3 FOC2 FOC1 FOC0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, I 0x00ce_0002 0x00cf_0002 0x00ce_0003 0x00cf_0003 0x00ce_0004 0x00cf_0004 0x00ce_0005 0x00cf_0005 Timer Output Compare 3 Mask Register (TIMOC3M) See page 302. Timer Output Compare 3 Data Register (TIMOC3D) See page 303. Timer Counter Register High (TIMCNTH) See page 304. Timer Counter Register Low (TIMCNTL) See page 304. Read: 0 0 0 0 Write: OC3M3 OC3M2 OC3M1 OC3M0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 Write: OC3D3 OC3D2 OC3D1 OC3D0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0x00ce_0006 0x00cf_0006 Timer System Control Register 1 (TIMSCR1) See page 305. Read: 0 0 0 0 0 0 TIMEN TFFCA Write: Reset: 0 0 0 0 0 0 0 0 P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception. Figure 2-2. Register Summary (Sheet 28 of 34) MMC2107 – Rev. 2.0 Technical Data MOTOROLA System Memory Map 81 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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