MMC2107 - Freescale Semiconductor

Timer Modules (TIM1 and TIM2)
Freescale Semiconductor, Inc.
15.7.17 Pulse Accumulator Counter Registers
Address: TIM1 — 0x00ce_001a
TIM2 — 0x00cf_001a
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
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Freescale Semiconductor, I
NOTE:
Reset: 0 0 0 0 0 0 0 0
Figure 15-21. Pulse Accumulator Counter Register High
(TIMPACNTH)
Address: TIM1 — 0x00ce_001b
TIM2 — 0x00cf_001b
Read:
Write:
Read: Anytime
Write: Anytime
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Reset: 0 0 0 0 0 0 0 0
Figure 15-22. Pulse Accumulator Counter Register Low
(TIMPACNTL)
These registers contain the number of active input edges on the PAI pin
since the last reset.
Reading the pulse accumulator counter registers immediately after an
active edge on the PAI pin may miss the last count since the input first
has to be synchronized with the bus clock.
To ensure coherent reading of the PA counter, such that the counter
does not increment between back-to-back 8-bit reads, it is
recommended that only half-word (16-bit) accesses be used.
Technical Data MMC2107 – Rev. 2.0
318 Timer Modules (TIM1 and TIM2) MOTOROLA
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