MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
18.9.3.9 State Machine
The state machine receives the QCLK, RST, STOP, IST[1:0], BYP,
CHAN[5:0], and START CONV. signals, from which it generates all
timing to perform an A/D conversion. The start-conversion signal
(START CONV.) indicates to the A/D converter that the desired channel
has been sent to the MUX. IST[1:0] indicates the desired sample time.
BYP indicates whether to bypass the sample amplifier. The
end-of-conversion (EOC) signal notifies the queue control logic that a
result is available for storage in the result RAM.
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18.10 Digital Control
The digital control subsystem includes the control logic to sequence the
conversion activity, the clock and periodic/interval timer, control and
status registers, the conversion command word table RAM, and the
result word table RAM.
The central element for control of the QADC conversions is the 64-entry
conversion command word (CCW) table. Each CCW specifies the
conversion of one input channel. Depending on the application, one or
two queues can be established in the CCW table. A queue is a scan
sequence of one or more input channels. By using a pause mechanism,
subqueues can be created in the two queues. Each queue can be
operated using one of several different scan modes. The scan modes for
queue 1 and queue 2 are programmed in the control registers QACR1
and QACR2. Once a queue has been started by a trigger event (any of
the ways to cause the QADC to begin executing the CCWs in a queue
or subqueue), the QADC performs a sequence of conversions and
places the results in the result word table.
18.10.1 Queue Priority Timing Examples
This subsection describes the QADC priority scheme when trigger
events on two queues overlap or conflict.
Technical Data MMC2107 – Rev. 2.0
450 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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