MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
During the stop mode, the CWP is reset to 0, since the control
registers and the analog logic are reset. When the debug mode is
entered, the CWP is unchanged; it points to the last executed CCW.
18.8.6.2 QADC Status Register 1
Stop mode resets the register ($3f3f)
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Freescale Semiconductor, I
Address: 0x00ca_0012 and 0x00ca_0013
Bit 15 14 13 12 11 10 9 Bit 8
Read: 0 0 CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10
Write:
Reset: 0 0 1 1 1 1 1 1
Read: Anytime
Write: Never
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20
Write:
Reset: 0 0 1 1 1 1 1 1
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-13. QADC Status Register 1 (QASR1)
CWPQ1[5:0] — Queue 1 Command Word Pointer Field
CWPQ1[5:0] allows the software to know what CCW was last
completed for queue 1. This field is a software read-only field, and
write operations have no effect. CWPQ1 allows software to read the
last executed CCW in queue 1, regardless of which queue is active.
The CWPQ1[5:0] field is a CCW word pointer with a valid range of 0
to 63 (0x3f).
In contrast to CWP, CPWQ1 is updated when the conversion result is
written. When the QADC finishes a conversion in queue 1, both the
result register is written and the CWPQ1 is updated.
Finally, when queue 1 operation is terminated after a CCW is read
that is defined as BQ2, CWP points to BQ2 while CWPQ1 points to
the last CCW queue 1.
Technical Data MMC2107 – Rev. 2.0
436 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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