MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
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Freescale Semiconductor, I
The two most significant bits are associated primarily with queue 1,
and the remaining two bits are associated with queue 2. Since the
priority scheme between the two queues causes the status to be
interlinked, the status bits are considered as one 4-bit field.
Table 18-8 shows the bits in the QS field and how they affect the
status of queue 1 and queue 2.
One or both queues may be in the idle state. When a queue is idle,
CCWs are not being executed for that queue, the queue is not in the
pause state, and there is not a trigger pending.
The idle state occurs when a queue is disabled, when a queue is in a
reserved mode, or when a queue is in a valid queue operating mode
awaiting a trigger event to initiate queue execution.
QS[9:6]
Table 18-8. Queue Status
Queue 1/Queue 2 States
0000 Queue 1 idle, queue 2 idle
0001 Queue 1 idle, queue 2 paused
0010 Queue 1 idle, queue 2 active
0011 Queue 1 idle, queue 2 trigger pending
0100 Queue 1 paused, queue 2 idle
0101 Queue 1 paused, queue 2 paused
0110 Queue 1 paused, queue 2 active
0111 Queue 1 paused, queue 2 trigger pending
1000 Queue 1 active, queue 2 idle
1001 Queue 1 active, queue 2 paused
1010 Queue 1 active, queue 2 suspended
1011 Queue 1 active, queue 2 trigger pending
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
A queue is in the active state when a valid queue operating mode is
selected, when the selected trigger event has occurred, or when the
QADC is performing a conversion specified by a CCW from that
queue.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 433
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