MMC2107 - Freescale Semiconductor

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Freescale Semiconductor, Inc. Queued Analog-to-Digital Converter (QADC) Table 18-17. Error Resulting From Input Leakage (I Off ) Source Impedance Leakage Value (10-Bit Conversions) 100 nA 200 nA 500 nA 1000 nA 1 kΩ — — 0.1 counts 0.2 counts 10 kΩ 0.2 counts 0.4 counts 1 counts 2 counts 100 kΩ 2 counts 4 count 10 counts 20 counts nc... Freescale Semiconductor, I 18.12 Interrupts 18.12.1 Interrupt Operation The four interrupt lines are outputs of the module and have no priority or arbitration within the module. QADC inputs can be monitored by polling or by using interrupts. When interrupts are not needed, software can disable the pause and completion interrupts and monitor the completion flag and the pause flag for each queue in the status register (QASR). In other words, flag bits can be polled to determine when new results are available. Table 18-18 shows the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. Queue Queue 1 Queue 2 Table 18-18. QADC Status Flags and Interrupt Sources Queue Activity Status Flag Interrupt Enable Bit Result written to last CCW in queue 1 CF1 CIE1 Result written for a CCW with pause bit set in queue 1 PF1 PIE1 Result written to last CCW in queue 2 CF2 CIE2 Result written for a CCW with pause bit set in queue 2 PF2 PIE2 If interrupts are enabled for an event, the QADC requests interrupt service when the event occurs. Using interrupts does not require continuously polling the status flags to see if an event has taken place. Technical Data MMC2107 – Rev. 2.0 500 Queued Analog-to-Digital Converter (QADC) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Queued Analog-to-Digital Converter (QADC) Interrupts However, status flags must be cleared after an interrupt is serviced, in to disable the interrupt request In both polled and interrupt-driven operating modes, status flags must be re-enabled after an event occurs. Flags are re-enabled by clearing appropriate QASR bits in a particular sequence. The register must first be read, then 0s must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. nc... Freescale Semiconductor, I 18.12.2 Interrupt Sources The QADC includes four sources of interrupt requests, each of which is separately enabled. Each time the result is written for the last conversion command word (CCW) in a queue, the completion flag for the corresponding queue is set, and when enabled, an interrupt request is generated. In the same way, each time the result is written for a CCW with the pause bit set, the queue pause flag is set, and when enabled, an interrupt request is generated. Refer to Table 18-18. The pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Queued Analog-to-Digital Converter (QADC) 501 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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