MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
System Memory Map
Address Map
Table 2-1. Register Address Location Map (1)
Base Address (Hex)
0x00c0_0000
0x00c1_0000
0x00c2_0000
0x00c3_0000
0x00c4_0000
Usage
Ports (2) (PORTS)
Chip configuration (CCM)
Chip selects (CS)
Clocks (CLOCK)
Reset (RESET)
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0x00c5_0000
0x00c6_0000
0x00c7_0000
0x00c8_0000
0x00c9_0000
0x00ca_0000
0x00cb_0000
0x00cc_0000
0x00cd_0000
0x00ce_0000
0x00cf_0000
0x00d0_0000
Interrupt controller (INTC)
Edge port (EPORT)
Watchdog timer (WDT)
Programmable interrupt timer 1 (PIT1)
Programmable interrupt timer 2 (PIT2)
Queued analog-to-digital converter (QADC)
Serial peripheral interface (SPI)
Serial communications interface 1 (SCI1)
Serial communications interface 2 (SCI2)
Timer 1 (TIM1)
Timer 2 (TIM2)
FLASH registers (CMFR)
1. See module sections for details of how much of each block is being decoded. Accesses to
addresses outside the module memory maps (and also the reserved area
0x00d1_0000–0x7fff_ffff) will not be responded to and will result in a bus monitor transfer
error exception.
2. The port register space is mirrored/repeated in the 64-Kbyte block. This allows the full
64-Kbyte block to be decoded and used to execute an external access to a port
replacement unit in emulation mode.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA System Memory Map 53
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