MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
overrun. As with all continuous-scan queue operating modes, software
action is not needed between trigger events. Since both queues may be
triggered by the periodic/interval timer, see 18.10.9 Periodic/Interval
Timer for a summary of periodic/interval timer reset conditions.
Software enables the completion interrupt when using the periodic timer
continuous-scan mode. When the interrupt occurs, the software knows
that the periodically collected analog results have just been taken. The
software can use the periodic interrupt to obtain nonanalog inputs as
well, such as contact closures, as part of a periodic look at all inputs.
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Freescale Semiconductor, I
18.10.8 QADC Clock (QCLK) Generation
NOTE:
CAUTION:
Figure 18-42 is a block diagram of the clock subsystem. The QCLK
provides the timing for the A/D converter state machine which controls
the timing of the conversion. The QCLK is also the input to a 17-stage
binary divider which implements the periodic/interval timer. To retain the
specified analog conversion accuracy, the QCLK frequency (f QCLK )
must be within the tolerance specified in Section 22. Electrical
Specifications.
Before using the QADC, the software must initialize the prescaler with
values that put the QCLK within the specified range. Though most
software applications initialize the prescaler once and do not change it,
write operations to the prescaler fields are permitted.
For software compatibility with earlier versions of QADC, the definition of
PSL, PSH, and PSA have been maintained. However, the requirements
on minimum time and minimum low time no longer exist.
A change in the prescaler value while a conversion is in progress is likely
to corrupt the result from any conversion in progress. Therefore, any
prescaler write operation should be done only when both queues are in
the disabled modes.
Technical Data MMC2107 – Rev. 2.0
476 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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