MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
List of Figures
Figure Title Page
18-49 Gated Mode, Continuous Scan Timing . . . . . . . . . . . . . . .491
18-50 Star-Ground at the Point of Power Supply Origin. . . . . . . .493
18-51 Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . .494
18-52 Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . .494
18-53 External Multiplexing of Analog Signal Sources. . . . . . . . .496
18-54 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . .497
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19-1 Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
19-2 Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
19-3 Master Mode — 1-Clock Read and Write Cycle. . . . . . . . .515
19-4 Master Mode — 2-Clock Read and Write Cycle. . . . . . . . .515
19-5 Internal (Show) Cycle Followed . . . . . . . . . . . . . . . . . . . . . . . .
by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
19-6 Internal (Show) Cycle Followed
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
20-1 Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .523
20-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
20-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
20-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
20-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
21-1 Top-Level Tap Module and Low-Level (OnCE)
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
21-2 Top-Level TAP Controller State Machine. . . . . . . . . . . . . .540
21-3 IDCODE Register Bit Specification . . . . . . . . . . . . . . . . . .545
21-4 OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
21-5 Low-Level (OnCE) Tap Module Data Registers (DRs). . . .554
21-6 OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21-7 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .559
21-8 OnCE Command Register (OCMR) . . . . . . . . . . . . . . . . . .562
21-9 OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . .564
21-10 OnCE Status Register (OSR). . . . . . . . . . . . . . . . . . . . . . .568
21-11 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . .570
21-12 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
21-13 CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . .576
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA List of Figures 35
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