MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
Receiver
After an entire frame shifts into the receive shift register, the data portion
of the frame transfers to SCIDRH and SCIDRL. The RDRF flag is set,
indicating that the received data can be read. If the RIE bit is also set,
RDRF generates an interrupt request.
16.12.3 Data Sampling
nc...
Freescale Semiconductor, I
RXD
SAMPLES
RT CLOCK
The receiver samples the RXD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock resynchronizes:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a 0 preceded by three 1s. When the falling edge of a possible start bit
occurs, the RT clock begins to count to 16.
START BIT
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
LSB
RT CLOCK COUNT
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RESET RT CLOCK
Figure 16-16. Receiver Data Sampling
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 357
For More Information On This Product,
Go to: www.freescale.com