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MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

Queued Analog-to-Digital Converter (QADC)<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

Only one queue can be active at a time. Either or both queues can be<br />

in the paused state. A queue is paused when the previous CCW<br />

executed from that queue had the pause bit set. The QADC does not<br />

execute any CCWs from the paused queue until a trigger event<br />

occurs. Consequently, the QADC can service queue 2 while queue 1<br />

is paused.<br />

Only queue 2 can be in the suspended state. When a trigger event<br />

occurs on queue 1 while queue 2 is executing, the current queue 2<br />

conversion is aborted. The queue 2 status is reported as suspended.<br />

Queue 2 transitions back to the active state when queue 1 becomes<br />

idle or paused.<br />

A trigger pending state is required since both queues cannot be active<br />

at the same time. The status of queue 2 is changed to trigger pending<br />

when a trigger event occurs for queue 2 while queue 1 is active. In the<br />

opposite case, when a trigger event occurs for queue 1 while queue 2<br />

is active, queue 2 is aborted and the status is reported as queue 1<br />

active, queue 2 suspended. So due to the priority scheme, only<br />

queue 2 can be in the trigger pending state.<br />

Two transition cases cause the queue 2 status to be trigger pending<br />

before queue 2 is shown to be in the active state. When queue 1 is<br />

active and there is a trigger pending on queue 2, after queue 1<br />

completes or pauses, queue 2 continues to be in the trigger pending<br />

state for a few clock cycles. The fleeting status conditions are:<br />

• queue 1 idle with queue 2 trigger pending<br />

• queue 1 paused with queue 2 trigger pending<br />

Figure 18-12 displays the status conditions of the queue status field<br />

as the QADC goes through the transition from queue 1 active to<br />

queue 2 active.<br />

The queue status field is affected by the stop mode. Since all of the<br />

analog logic and control registers are reset, the queue status field is<br />

reset to queue 1 idle, queue 2 idle.<br />

During the debug mode, the queue status field is not modified. The<br />

queue status field retains the status it held prior to freezing. As a<br />

result, the queue status can show queue 1 active, queue 2 idle, even<br />

though neither queue is being executed during freeze.<br />

Technical Data <strong>MMC2107</strong> – Rev. 2.0<br />

434 Queued Analog-to-Digital Converter (QADC) MOTOROLA<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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