MMC2107 - Freescale Semiconductor

Clock Module
Freescale Semiconductor, Inc.
10.8.3.1 PLL Loss of Lock Conditions
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are
set. If the MFD is changed, or if an unexpected loss of lock condition
occurs, the LOCK and LOCKS flags are negated. While the PLL is in the
non-locked condition, the system clocks continue to be sourced from the
PLL as the PLL attempts to relock. Consequently, during the relocking
process, the system clocks frequency is not well defined and may
exceed the maximum system frequency, violating the system clock
timing specifications.
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Freescale Semiconductor, I
10.8.3.2 PLL Loss of Lock Reset
10.8.4 Loss of Clock Detection
However, once the PLL has relocked, the LOCK flag is set. The LOCKS
flag remains cleared if the loss of lock is unexpected. The LOCKS flag is
set when the loss of lock is caused by changing MFD. If the PLL is
intentionally disabled during stop mode, then after exit from stop mode,
the LOCKS flag reflects the value prior to entering stop mode once lock
is regained.
If the LOLRE bit in SYNCR is set, a loss of lock condition asserts reset.
Reset reinitializes the LOCK and LOCKS flags. Therefore, software
must read the LOL bit in reset status register (RSR) to determine if a loss
of lock caused the reset. See 5.6.2 Reset Status Register.
To exit reset in PLL mode, the reference must be present, and the PLL
must achieve lock.
In external clock mode, the PLL cannot lock. Therefore, a loss of lock
condition cannot occur, and the LOLRE bit has no effect.
The LOCEN bit in SYNCR enables the loss of clock detection circuit to
monitor the input clocks to the phase and frequency detector (PFD).
When either the reference or feedback clock frequency falls below the
minimum frequency, the loss of clock circuit sets the sticky LOCS flag in
SYNSR.
NOTE:
In external clock mode, the loss of clock circuit is disabled.
Technical Data MMC2107 – Rev. 2.0
238 Clock Module MOTOROLA
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