MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Interrupts
15.10.2 Pulse Accumulator Overflow (PAOVF)
PAOVF is set when the 16-bit pulse accumulator rolls over from $FFFF
to $0000. If the PAOVI bit in TIMPACTL is also set, PAOVF generates
an interrupt request. Clear PAOVF by writing a 1 to it.
NOTE:
When the fast flag clear all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in TIMPAFLG.
15.10.3 Pulse Accumulator Input (PAIF)
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NOTE:
15.10.4 Timer Overflow (TOF)
NOTE:
PAIF is set when the selected edge is detected at the PAI pin. In event
counter mode, the event edge sets PAIF. In gated time accumulation
mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the
PAI bit in TIMPACTL is also set, PAIF generates an interrupt request.
Clear PAIF by writing a 1 to it.
When the fast flag clear all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in TIMPAFLG.
TOF is set when the timer counter rolls over from $FFFF to $0000. If the
TOI bit in TIMSCR2 is also set, TOF generates an interrupt request.
Clear TOF by writing a 1 to it.
When the timer channel 3 registers contain $FFFF and TCRE is set,
TOF never gets set even though the timer counter registers go from
$FFFF to $0000.
When the fast flag clear all bit, TFFCA, is set, any access to the timer
counter registers clears timer flag register 2. The TFFCA bit is in timer
system control register 1 (TIMSCR1).
When TOF is set, it does not inhibit future overflow events.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Timer Modules (TIM1 and TIM2) 327
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