MMC2107 - Freescale Semiconductor

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Timer Modules (TIM1 and TIM2) Freescale Semiconductor, Inc. 15.7.1 Timer Input Capture/Output Compare Select Register Address: TIM1 — 0x00ce_0000 TIM2 — 0x00cf_0000 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 Write: IOS3 IOS2 IOS1 IOS0 Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I Read: Anytime; always read $00 Write: Anytime = Writes have no effect and the access terminates without a transfer error exception. Figure 15-2. Timer Input Capture/Output Compare Select Register (TIMIOS) IOS[3:0] — I/O Select Bits The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels. 1 = Output compare enabled 0 = Input capture enabled Technical Data MMC2107 – Rev. 2.0 300 Timer Modules (TIM1 and TIM2) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Timer Modules (TIM1 and TIM2) Memory Map and Registers 15.7.2 Timer Compare Force Register Address: TIM1 — 0x00ce_0001 TIM2 — 0x00cf_0001 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: FOC3 FOC2 FOC1 FOC0 Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I Read: Anytime Write: Anytime = Writes have no effect and the access terminates without a transfer error exception. Figure 15-3. Timer Compare Force Register (TIMCFORC) FOC[3:0] — Force Output Compare Bits Setting an FOC bit causes an immediate output compare on the corresponding channel. Forcing an output compare does not set the output compare flag. 1 = Force output compare 0 = No effect NOTE: A successful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Timer Modules (TIM1 and TIM2) 301 For More Information On This Product, Go to: www.freescale.com
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