MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Memory Map and Registers
17.7.4 SPI Status Register
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Freescale Semiconductor, I
Address: 0x00cb_0003
Read: Anytime
Bit 7 6 5 4 3 2 1 Bit 0
Read: SPIF WCOL 0 MODF 0 0 0 0
Write:
Reset: 0 0 0 0 0 0 0 0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 17-5. SPI Status Register (SPISR)
Write: Has no meaning or effect
SPIF — SPI Interrupt Flag
The SPIF flag is set after the eighth SCK cycle in a transmission when
received data transfers from the shift register to SPIDR. If the SPIE bit
is also set, SPIF generates an interrupt request. Once SPIF is set, no
new data can be transferred into SPIDR until SPIF is cleared. Clear
SPIF by reading SPISR with SPIF set and then accessing SPIDR.
Reset clears SPIF.
1 = New data available in SPIDR
0 = No new data available in SPIDR
WCOL — Write Collision Flag
The WCOL flag is set when software writes to SPIDR during a
transmission. Clear WCOL by reading SPISR with WCOL set and
then accessing SPIDR. Reset clears WCOL.
1 = Write collision
0 = No write collision
MODF — Mode Fault Flag
The MODF flag is set when the SS pin of a master SPI is driven low
and the SS pin is configured as a mode-fault input. If the SPIE bit is
also set, MODF generates an interrupt request. A mode fault clears
the SPE, MSTR, and DDRSP[2:0] bits. Clear MODF by reading
SPISR with MODF set and then writing to SPICR1. Reset clears
MODF.
1 = Mode fault
0 = No mode fault
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Peripheral Interface Module (SPI) 381
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