MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Interrupts
However, status flags must be cleared after an interrupt is serviced, in
to disable the interrupt request
In both polled and interrupt-driven operating modes, status flags must be
re-enabled after an event occurs. Flags are re-enabled by clearing
appropriate QASR bits in a particular sequence. The register must first
be read, then 0s must be written to the flags that are to be cleared. If a
new event occurs between the time that the register is read and the time
that it is written, the associated flag is not cleared.
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Freescale Semiconductor, I
18.12.2 Interrupt Sources
The QADC includes four sources of interrupt requests, each of which is
separately enabled. Each time the result is written for the last conversion
command word (CCW) in a queue, the completion flag for the
corresponding queue is set, and when enabled, an interrupt request is
generated. In the same way, each time the result is written for a CCW
with the pause bit set, the queue pause flag is set, and when enabled,
an interrupt request is generated. Refer to Table 18-18.
The pause and complete interrupts for queue 1 and queue 2 have
separate interrupt vector levels, so that each source can be separately
serviced.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 501
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