MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
PSA — Prescaler Add Clock Tick Bit
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
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Freescale Semiconductor, I
PSL[2:0] — Prescaler Clock Low Time Field
The PSL field selects the QCLK low time in the prescaler.
See Section 22. Electrical Specifications for f QCLK
values.
To keep the QCLK within the specified range, the PSL field selects the
low time of the QCLK, which can range from one to eight system clock
cycles. The minimum low time for the clock is specified as t PSL
.
Table 18-4 displays the bits in PSL field which enable a range of
QCLK low times.
Table 18-4. Prescaler Clock Low Times
PSL[2:0]
QCLK Low Time
000 1 system clock cycle
001 2 system clock cycles
010 3 system clock cycles
011 4 system clock cycles
100 5 system clock cycles
101 6 system clock cycles
110 7 system clock cycles
111 8 system clock cycles
Technical Data MMC2107 – Rev. 2.0
418 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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