MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
Memory Map and Registers
WAKE — Wakeup Bit
This read/write bit selects the condition that wakes up the SCI
receiver when it has been placed in a standby state by setting the
RWU bit in SCICR2. When WAKE is set, a logic 1 (address mark) in
the most significant bit position of a received data character wakes the
receiver. An idle condition on the RXD pin does so when WAKE = 0.
Reset clears WAKE.
1 = Address mark receiver wakeup
0 = Idle line receiver wakeup
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ILT — Idle Line Type Bit
This read/write bit determines when the receiver starts counting logic
1s as idle character bits. The counting begins either after the start bit
or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an
idle character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears ILT.
1 = Idle frame bit count begins after stop bit.
0 = Idle frame bit count begins after start bit.
PE — Parity Enable Bit
This read/write bit enables the parity function. When enabled, the
parity function inserts a parity bit in the most significant bit position of
an SCI data word. Reset clears PE.
1 = Parity function enabled
0 = Parity function disabled
PT — Parity Type Bit
This read/write bit selects even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s
sets the parity bit. With odd parity, an odd number of 1s clears the
parity bit and an even number of 1s sets the parity bit. Reset clears
PT.
1 = Odd parity when PE = 1
0 = Even parity when PE = 1
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 339
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