MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Chip Select Module
Memory Map and Registers
asserted in the clock cycle following the start of the cycle access,
resulting in one-clock transfers. A WS configured for one wait state
means that the internal cycle termination signal is asserted two clock
cycles after the start of the cycle access.
Since the internal cycle termination signal is asserted internally after
the programmed number of wait states, software can adjust the bus
timing to accommodate the access speed of the external device. With
up to seven possible wait states, even slow devices can be interfaced
with the MCU.
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Freescale Semiconductor, I
WS[2:0]
Table 20-3. Chip Select Wait States Encoding
Number of Wait States
WWS = 0 WWS = 1
Read Access Write Access Read Access Write Access
000 0 0 0 1
001 1 1 1 2
010 2 2 2 3
011 3 3 3 4
100 4 4 4 5
101 5 5 5 6
110 6 6 6 7
111 7 7 7 8
TAEN — Transfer Acknowledge Enable Bit
The TAEN bit determines whether the internal cycle termination
signal is asserted by the chip select logic when accesses occur to the
address range defined by the corresponding chip select. When TAEN
is 0, an external device is responsible for asserting the external TA pin
to terminate the bus access. When TAEN is 1, the chip select logic
asserts the internal cycle termination signal after a time determined
by the programmed number of wait states. When TAEN is 1, external
logic can still terminate the access before the internal cycle
termination signal is asserted by asserting the external TA pin.
1 = Internal cycle termination signal asserted by chip select logic
0 = Internal cycle termination signal asserted by external logic
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Chip Select Module 529
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