MMC2107 - Freescale Semiconductor

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Freescale Semiconductor, Inc. Queued Analog-to-Digital Converter (QADC) 18.8.4 Port QA Data Direction Register nc... Freescale Semiconductor, I NOTE: The port data direction register (DDRQA) is associated with the port QA digital I/O pins. The bidirectional pins may have somewhat higher leakage and capacitance specifications. Any bit in this register set to 1 configures the corresponding pin as an output. Any bit in this register cleared to 0 configures the corresponding pin as an input. The software is responsible for ensuring that DDR bits are not set to 1 on pins used for analog inputs. When the DDR bit is set to 1 and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are ignored for the bits corresponding to PQA[1:0], the two multiplexed address (MA[1:0]) output pins. The MA[1:0] pins are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs are driven. The data returned during a port data register read is the value of MA[1:0], regardless of the data direction setting. Similarly, when the external trigger pins are assigned to port pins and external trigger queue operating mode is selected, the data direction setting for the corresponding pins, PQA3 or PQA4, is ignored. The port pins are forced to be digital inputs for ETRIG1 and/or ETRIG2. The data driven during a port data register read is the actual value of the pin, regardless of the data direction setting. Use caution when mixing digital and analog inputs. They should be isolated as much as possible. Rise and fall times should be as large as possible to minimize ac coupling effects. Since port QB is input-only, a data direction register is not needed. Therefore, the lower byte of the port data direction register is not implemented. Technical Data MMC2107 – Rev. 2.0 414 Queued Analog-to-Digital Converter (QADC) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Queued Analog-to-Digital Converter (QADC) Register Descriptions Address: 0x00ca_0008 and 0x00ca_0009 Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 0 Write: DDQA4 DDQA3 0 DDQA1 DDQA0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I Write: Reset: 0 0 0 0 0 0 0 0 = Writes have no effect and the access terminates without a transfer error exception. Figure 18-7. QADC Port QA Data Direction Register (DDRQA) Read: Anytime Write: Anytime except stop mode MMC2107 – Rev. 2.0 Technical Data MOTOROLA Queued Analog-to-Digital Converter (QADC) 415 For More Information On This Product, Go to: www.freescale.com
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