MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
PIE1 — Queue 1 Pause Interrupt Enable Bit
PIE1 enables an interrupt when queue 1 enters the pause state. The
interrupt request is initiated when conversion is complete for a CCW
that has the pause bit set.
1 = Enable an interrupt after an end-of-conversion for queue 1
which has the pause bit set.
0 = Disable the pause interrupt associated with queue 1.
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Freescale Semiconductor, I
SSE1 — Queue 1 Single-Scan Enable Bit
SSE1 enables a single-scan of queue 1 to start after a trigger event
occurs. The SSE1 bit may be set to a 1 during the same write cycle
when the MQ1 bits are set for one of the single-scan queue operating
modes. The single-scan enable bit can be written as a 1 or a 0, but is
always read as a 0, unless a test mode is selected. The SSE1 bit
enables a trigger event to initiate queue execution for any single-scan
operation on queue 1.The QADC clears the SSE1 bit when the
single-scan is complete.
1 = Accept a trigger event to start queue 1 in a single-scan mode.
0 = Trigger events are not accepted for single-scan modes.
MQ1[12:8] — Queue 1 Operating Mode Field
The MQ1 field selects the queue operating mode for queue 1.
Table 18-5 shows the bits in the MQ1 field which enable different
queue 1 operating modes.
MQ1[12:8]
Table 18-5. Queue 1 Operating Modes
Operating Mode
00000 Disabled mode, conversions do not occur
00001 Software-triggered single-scan mode (started with SSE1)
00010 External-trigger rising-edge single-scan mode
00011 External-trigger falling-edge single-scan mode
00100 Interval timer single-scan mode: time = QCLK period × 2 7
00101 Interval timer single-scan mode: time = QCLK period × 2 8
00110 Interval timer single-scan mode: time = QCLK period × 2 9
00111 Interval timer single-scan mode: time = QCLK period × 2 10
01000 Interval timer single-scan mode: time = QCLK period × 2 11
Technical Data MMC2107 – Rev. 2.0
420 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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