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MMC2107 - Freescale Semiconductor

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Non-Volatile Memory FLASH (CMFR)<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

To improve system performance, the BIU accesses information in the<br />

array at 32 bytes per access. These 32 bytes are copied in a read page<br />

buffer aligned to the low-order addresses. A CMFR array contains two<br />

non-overlapping read page buffers. The first read page buffer is<br />

associated to the lower array blocks. The second read page buffer is<br />

associated to the higher array blocks. Read access time of the data in<br />

the current read page buffers is one system clock, while the time to read<br />

a new page into a page buffer and access the required information is two<br />

system clocks. These accesses are known as an on-page read and an<br />

off-page read, respectively. To prevent the BIU from accessing an<br />

unnecessary page from the array, the CMFR monitors the address to<br />

determine if the required information is in one of the two current read<br />

page buffers and the access is valid for the module. This strategy allows<br />

the CMFR to have a two-clock read for an off-page access and one-clock<br />

for an on-page access. In normal operation write accesses to the CMFR<br />

array are not allowed, a write access causes a bus error.<br />

The CMFR requires an external program or erase voltage, V PP , to<br />

program or erase the array. Special control logic is included to require a<br />

specific series of read and write accesses.<br />

To improve program performance, the CMFR programs up to eight<br />

unique 64-byte pages simultaneously in eight separate array blocks.<br />

These 64 bytes are aligned to the low-order addresses to form a<br />

program page buffer.<br />

Each of the pages being programmed simultaneously are located at the<br />

same block offset address. Erasing is performed on one or more of the<br />

selected array blocks simultaneously.<br />

An extra row (256 bytes) of the CMFR array is used to provide reset<br />

configuration information and is called shadow information. This row<br />

may be accessed by setting the SIE bit in the CMFR module<br />

configuration register and accessing the CMFR array. The shadow<br />

information is in the lowest array block 0 of the CMFR array. Note that<br />

the shadow row is erased with block 0.<br />

Technical Data <strong>MMC2107</strong> – Rev. 2.0<br />

184 Non-Volatile Memory FLASH (CMFR) MOTOROLA<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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