MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
Reset
16.16 Reset
Reset initializes the SCI registers to a known startup state as described
in 16.7 Memory Map and Registers.
16.17 Interrupts
Table 16-10 lists the five interrupt requests associated with each SCI
module.
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Freescale Semiconductor, I
16.17.1 Transmit Data Register Empty
16.17.2 Transmission Complete
Table 16-10. SCI Interrupt Request Sources
Source Flag Enable Bit
Transmitter
Receiver
TDRE
TC
RDRF
OR
IDLE
The TDRE flag is set when the transmit shift register receives a byte from
the SCI data register. It signals that SCIDRH and SCIDRL are empty and
can receive new data to transmit. If the TIE bit in SCICR2 is also set,
TDRE generates an interrupt request. Clear TDRE by reading SCISR1
and then writing to SCIDRL. Reset sets TDRE.
The TC flag is set when TDRE = 1 and no data, preamble, or break
frame is being transmitted. It signals that no transmission is in progress.
If the TCIE bit is set in SCICR2, TC generates an interrupt request.
When TC is set, the TXD pin is idle (logic 1). TC is cleared automatically
when a data, preamble, or break frame is queued. Clear TC by reading
SCISR1 with TC set and then writing to the SCIDRL register. TC cannot
be cleared while a transmission is in progress.
TIE
TCIE
RIE
RIE
ILIE
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 369
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