MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Programmable Interrupt Timer Modules (PIT1 and PIT2)
14.6 Memory Map and Registers
This subsection describes the memory map and register structure for
PIT1 and PIT2.
14.6.1 Memory Map
Refer to Table 14-1 for a description of the memory map.
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PIT1
Address
14.6.2 Registers
This device has two programmable interrupt timers. PIT1 has a base
address located at 0x00c8_0000. PIT2 base address is 0x00c9_0000.
Table 14-1. Programmable Interrupt Timer Modules Memory Map
PIT2
Address
Bits 15–8 Bits 7–0 Access (1)
0x00c8_0000 0x00c9_0000 PIT control and status register (PCSR) S
0x00c8_0002 0x00c9_0002 PIT modulus register (PMR) S
0x00c8_0004 0x00c9_0004 PIT count register (PCNTR) S/U
0x00c8_0006 0x00c9_0006 Unimplemented (2) —
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
only addresses have no effect and result in a cycle termination transfer error.
2. Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
The PIT programming model consists of these registers:
• The PIT control and status register (PCSR) configures the timer’s
operation.
• The PIT modulus register (PMR) determines the timer modulus
reload value.
• The PIT count register (PCNTR) provides visibility to the counter
value.
Technical Data MMC2107 – Rev. 2.0
284 Programmable Interrupt Timer Modules (PIT1 and PIT2) MOTOROLA
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