MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
TME — Trace Mode Enable Bit
TME enables trace operation. Test logic reset clears the TME bit.
Trace operation is also affected by the SQC field.
1 = Trace operation enabled
0 = Trace operation disabled
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Freescale Semiconductor, I
FRZC — Freeze Control Bit
This control bit is used in conjunction with memory breakpoint B
registers to select between asserting a breakpoint condition when a
memory breakpoint B occurs or freezing the PC FIFO from further
updates when memory breakpoint B occurs while allowing the CPU to
continue execution. The PC FIFO remains frozen until the FRZO bit
in the OSR is cleared.
1 = Memory breakpoint B occurrence freezes PC FIFO and does
not assert breakpoint condition.
0 = Memory breakpoint B occurrence asserts breakpoint condition.
RCB and RCA — Memory Breakpoint B and A Range Control Bits
RCB and RDA condition enabled memory breakpoint occurrences
happen when memory breakpoint matches are either within or outside
the range defined by memory base address and mask.
1 = Condition breakpoint on access outside of range
0 = Condition breakpoint on access within range
BCB4–BCB0 and BCA4–BCA0 — Memory Breakpoint B and A Control
Fields
The BCB and BCA fields enable memory breakpoints and qualify the
access attributes to select whether the breakpoint matches are
recognized for read, write, or instruction fetch (program space)
accesses. Test logic reset clears BCB4–BCB0 and BCA4–BCA0.
Technical Data MMC2107 – Rev. 2.0
566 JTAG Test Access Port and OnCE MOTOROLA
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