MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
Figure 18-43 and Table 18-15 show examples of QCLK
programmability. The examples include conversion times based on this
assumption:
Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
Figure 18-43 and Table 18-15 also show the conversion time calculated
for a single conversion in a queue. For other MCU system clock
frequencies and other input sample times, the same calculations can be
made.
nc...
Freescale Semiconductor, I
SYSTEM
CLOCK (f sys )
QCLK
EXAMPLE 1
QCLK
EXAMPLE 2
NOTE:
20 CYCLES
Figure 18-43. QADC Clock Programmability Examples
Table 18-15. QADC Clock Programmability
Control Register 0 Information
Example Number Frequency PSH PSL QCLK
(MHz)
Input Sample Time
IST = Binary 00
Conversion Time
(µs)
1 40 MHz 11 7 2.0 7.0
2 32 MHz 7 7 2.0 7.0
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
The MCU system clock frequency is the basis of the QADC timing. The
QADC requires that the system clock frequency be at least twice the
QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH
field selects the number of system clock cycles in the high phase of the
QCLK wave. The 3-bit PSL field selects the number of system clock
cycles in the low phase of the QCLK wave.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 479
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