MMC2107 - Freescale Semiconductor

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System Memory Map Freescale Semiconductor, Inc. Address Register Name Bit Number Bit 7 6 5 4 3 2 1 Bit 0 0x00c3_0003 Synthesizer Test Register (SYNTR) See page 233. Read: 0 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 Bit 31 30 29 28 27 26 25 Bit 24 0x00c3_0004 0x00c3_0005 0x00c3_0006 0x00c3_0007 Synthesizer Test Register 2 (SYNTR2) See page 234. Read: 0 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 nc... Freescale Semiconductor, I 0x00c3_0008 ↓ 0x00c3_ffff Reset (RESET) Unimplemented Bit 23 22 21 20 19 18 17 Bit 16 Read: 0 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 0 0 0 0 Write: RSVD9 Reset: 0 0 0 0 0 0 0 0 Read: Write: RSVD8 Bit 7 6 5 4 3 2 1 Bit 0 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD2 RSVD0 Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Access results in a bus monitor timeout generating an access termination transfer error. Bit 7 6 5 4 3 2 1 Bit 0 0x00c4_0000 Reset Control Register (RCR) See page 133. Read: Write: SOFTRST FRC- RSTOUT 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception. Figure 2-2. Register Summary (Sheet 11 of 34) Technical Data MMC2107 – Rev. 2.0 64 System Memory Map MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. System Memory Map Register Map Address Register Name Bit Number Bit 7 6 5 4 3 2 1 Bit 0 nc... Freescale Semiconductor, I 0x00c4_0001 0x00c4_0002 0x00c4_0003 0x00c4_0004 ↓ 0x00c4_ffff Interrupt Controller (INTC) 0x00c5_0000 0x00c5_0001 0x00c5_0002 0x00c5_0003 Reset Status Register (RSR) See page 134. Reset Test Register (RTR) See page 135. Reserved Unimplemented Interrupt Control Register (ICR) See page 157. Interrupt Status Register (ISR) See page 159. Read: 0 0 SOFT WDR POR EXT LOC LOL Write: Reset: 0 0 Reset dependent Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: Reset: 0 0 0 0 0 0 0 0 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Writes have no effect, reads return 0s, and the access terminates without a transfer error exception. Bit 7 6 5 4 3 2 1 Bit 0 Access results in a bus monitor timeout generating an access termination transfer error. Bit 15 14 13 12 11 10 9 Bit 8 AE FVE ME MFI 0 0 0 0 Reset: 1 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 Write: MASK4 MASK3 MASK2 MASK1 MASK0 Reset: 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: 0 0 0 0 0 0 INT FINT Write: Reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0 Write: Reset: 0 0 0 0 0 0 0 0 P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception. Figure 2-2. Register Summary (Sheet 12 of 34) MMC2107 – Rev. 2.0 Technical Data MOTOROLA System Memory Map 65 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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