MMC2107 - Freescale Semiconductor

Non-Volatile Memory FLASH (CMFR)
Freescale Semiconductor, Inc.
S2
T3
S3
T1 T2 T6
T4
RESET
S1
T7
S4
T8
T5
nc...
T9
S5
Freescale Semiconductor, I
State
S1
S2
Figure 9-8. Program State Diagram
Table 9-7. Program Interlock State Descriptions
Mode
Normal operation: Normal array reads and
register accesses. Block protect information
and pulse width timing control can be
modified.
First program hardware interlock write:
Normal read operation. Array accepts
programming writes. Normal register
accesses. CMFRCTL write cannot change
EHV. If write is to a register other than
CMFRMCR, no data is stored in program
page buffers; CMFR remains in S2.
Next
State
Transition Requirement
S2 T2 Write ERASE = 0 and SES = 1
S1
S3
T1 Write SES = 0 or master reset
T3
Hardware interlock: Successful programming
write to any array location. Latches selected
data word into programming page buffer;
address latched to select location to
program. Bit that has been written remains
in program buffer until another write to it, or
SES is cleared, or a program margin read
determines bit needs no modification by
program operation. If write is to a register
(except CMFRMCR), no data is stored in
program page buffers, and CMFR remains
in S2. Writing to CMFRMCR does not allow
array to be programmed.
Technical Data MMC2107 – Rev. 2.0
210 Non-Volatile Memory FLASH (CMFR) MOTOROLA
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