MMC2107 - Freescale Semiconductor

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Freescale Semiconductor, Inc. Serial Communications Interface Modules (SCI1 and SCI2) 16.7.4 SCI Status Register 1 Address: SCI1 — 0x00cc_0004 SCI2 — 0x00cd_0004 Bit 7 6 5 4 3 2 1 Bit 0 Read: TDRE TC RDRF IDLE OR NF FE PF Write: nc... Freescale Semiconductor, I Reset: 1 1 0 0 0 0 0 0 Read: Anytime = Writes have no effect and the access terminates without a transfer error exception. Figure 16-6. SCI Status Register 1 (SCISR1) Write: Has no meaning or effect TDRE — Transmit Data Register Empty Flag The TDRE flag is set when the transmit shift register receives a word from the SCI data register. It signals that the SCIDRH and SCIDRL are empty and can receive new data to transmit. If the TIE bit in the SCICR2 is also set, TDRE generates an interrupt request. Clear TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets TDRE. 1 = Transmit data register empty 0 = Transmit data register not empty TC — Transmit Complete Flag The TC flag is set when TDRE = 1 and no data, preamble, or break frame is being transmitted. It signals that no transmission is in progress. If the TCIE bit is set in SCICR2, TC generates an interrupt request. When TC is set, the TXD pin is idle (logic 1). TC is cleared automatically when a data, preamble, or break frame is queued. Clear TC by reading SCISR1 with TC set and then writing to SCIDRL. TC cannot be cleared while a transmission is in progress. Reset sets TC. 1 = No transmission in progress 0 = Transmission in progress Technical Data MMC2107 – Rev. 2.0 342 Serial Communications Interface Modules (SCI1 and SCI2) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Serial Communications Interface Modules (SCI1 and SCI2) Memory Map and Registers nc... Freescale Semiconductor, I NOTE: RDRF — Receive Data Register Full Flag The RDRF flag is set when the data in the receive shift register is transferred to SCIDRH and SCIDRL. It signals that the received data is available to the MCU. If the RIE bit is set in SCICR2, RDRF generates an interrupt request. Clear RDRF by reading the SCISR1 and then reading SCIDRL. Reset clears RDRF. 1 = Received data available in SCIDRH and SCIDRL 0 = Received data not available in SCIDRH and SCIDRL IDLE — Idle Line Flag The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive logic 1s appear on the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an interrupt request. Once IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCISR1 and then reading SCIDRL. Reset clears IDLE. 1 = Receiver idle 0 = Receiver active or idle since reset or idle since IDLE flag last cleared When RWU =1, an idle line condition does not set the IDLE flag. OR — Overrun Flag The OR flag is set if data is not read from SCIDRL before the receive shift register receives the stop bit of the next frame. This is a receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates an interrupt request. The data in the shift register is lost, but the data already in the SCIDRH and SCIDRL is not affected. Clear OR by reading SCISR1 and then reading SCIDRL. Reset clears OR. 1 = Overrun 0 = No overrun NF — Noise Flag The NF flag is set when the SCI detects noise on the receiver input. NF is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCISR1 and then reading SCIDRL. Reset clears NF. 1 = Noise 0 = No noise MMC2107 – Rev. 2.0 Technical Data MOTOROLA Serial Communications Interface Modules (SCI1 and SCI2) 343 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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