MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Clock Module
Memory Map and Registers
10.7.2 Register Descriptions
This subsection provides a description of the clock module registers.
10.7.2.1 Synthesizer Control Register
The synthesizer control register (SYNCR) is read/write always.
Address: 0x00c3_0000 and 0x00c3_0001
Bit 15 14 13 12 11 10 9 Bit 8
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Read:
Write:
LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0
Reset: 0 0 1 0 0 0 0 1
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPD0 RSVD1 RSVD0
Reset: 0 0 0 0 0 0 0 0
Figure 10-2. Synthesizer Control Register (SYNCR)
LOLRE — Loss of Lock Reset Enable Bit
The LOLRE bit determines how the system handles a loss of lock
indication. When operating in normal mode or 1:1 PLL mode, the PLL
must be locked before setting the LOLRE bit. Otherwise reset is
immediately asserted. To prevent an immediate reset, the LOLRE bit
must be cleared before writing the MFD[2:0] bits or entering stop
mode with the PLL disabled.
1 = Reset on loss of lock
0 = No reset on loss of lock
NOTE:
In external clock mode, the LOLRE bit has no effect.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Clock Module 227
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