MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Functional Description
After the 16th and final SCK edge:
• Data that was in the master SPIDR register is in the slave SPIDR.
Data that was in the slave SPIDR register is in the master SPIDR.
• The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
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Figure 17-11 shows the timing of a transmission with the CPHA bit set.
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
Freescale Semiconductor, I
BEGIN TRANSMISSION
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
MOSI/MISO
CHANGE OUTPUT
MOSI PIN
CHANGE OUTPUT
MISO PIN
SS PIN OUTPUT
MASTER ONLY
SLAVE SS PIN
MSB FIRST (LSBFE = 0):
LSB FIRST (LSBFE = 1):
t L
MSB
LSB
BIT 6
BIT 1
BIT 5
BIT 2
BIT 4
BIT 3
BIT 3
BIT 4
BIT 2
BIT 5
END TRANSMISSION
BIT 1
BIT 6
LSB
MSB
t T
t I
t L
MINIMUM 1/2 SCK
FOR t T , t L , t l
IF NEXT TRANSFER BEGINS HERE
Legend:
t L = Minimum leading time before the first SCK edge
t T = Minimum trailing time after the last SCK edge
t I = Minimum idling time between transmissions (minimum SS high time)
t L , t T , and t I are guaranteed for master mode and required for slave mode.
Figure 17-11. SPI Clock Format 1 (CPHA = 1)
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Peripheral Interface Module (SPI) 389
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