MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
The QADC automatically performs the conversions in the queue until a
pause or an end-of-queue condition is encountered. When a pause
occurs, queue execution stops until the timer interval elapses again, and
queue execution continues. When the queue execution reaches an
end-of-queue situation, the single-scan enable bit is cleared. Software
may set the single-scan enable bit again, allowing another scan of the
queue to be initiated by the interval timer.
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The interval timer generates a trigger event whenever the time interval
elapses. The trigger event may cause the queue execution to continue
following a pause, or may be considered a trigger overrun. Once the
queue execution is completed, the single-scan enable bit must be set
again to enable the timer to count again.
Normally, only one queue will be enabled for interval timer single-scan
mode and the timer will reset at the end-of-queue. However, if both
queues are enabled for either single-scan or continuous interval timer
mode, the end-of-queue condition will not reset the timer while the other
queue is active. In this case, the timer will reset when both queues have
reached end-of-queue. See 18.10.9 Periodic/Interval Timer for a
definition of interval timer reset conditions.
The interval timer single-scan mode can be used in applications which
need coherent results, for example:
• When it is necessary that all samples are guaranteed to be taken
during the same scan of the analog pins.
• When the interrupt rate in the periodic timer continuous-scan
mode would be too high.
• In sensitive battery applications, where the single-scan mode uses
less power than the software-initiated continuous-scan mode.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 471
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