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MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

External Bus Interface Module (EBI)<br />

Emulation Support<br />

D28 pin is driven low during reset configuration to disable the internal<br />

FLASH so that no conflict exists with the external memory device. It<br />

should be noted that at higher frequencies writes to external memories<br />

emulating the internal memories may require one clock for read<br />

accesses and two clocks for write accesses.<br />

Table 19-4. Emulation Mode Chip-Select Summary (1)<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

CSE1 CSE0 Indication in Emulation Mode<br />

1 1<br />

1 0<br />

0 1<br />

0 0<br />

1. CSE[1:0] is valid only for the duration of valid bus cycles or reset. Undefined otherwise.<br />

19.9.2 Internal Data Transfer Display (Show Cycles)<br />

Internal access to any register space (excluding ports)<br />

Reset state<br />

(0x00c1_0000:0x00ff_ffff)<br />

Internal access to ports register space<br />

(0x00c0_0000:0x00c0_ffff)<br />

Internal access not covered by CSE encoding = 11, 10<br />

(0x0000_0000:0x00bf_ffff; 0x0100_0000:0x07ff_ffff)<br />

External access<br />

(0x8000_0000 to 0xffff_ffff)<br />

Internal data transfers normally occur without showing the internal data<br />

bus activity on the external data bus. For debugging purposes, however,<br />

it may be desirable to have internal cycle data appear on the external<br />

bus. These external bus cycles are referred to as show cycles and are<br />

distinguished from normal external cycles by the fact that OE and<br />

EB[3:0] remain negated.<br />

Regardless of whether show cycles are enabled, the EBI drives the<br />

address bus, TC[2:0], TSIZ[1:0] and R/W signals, indicating the internal<br />

cycle activity. When show cycles are disabled, D[31:0] remains in a high<br />

impedance state. When show cycles are enabled, OE and EB[3:0]<br />

remain negated while the internal data is presented on D[31:0] on the<br />

first clock tick after the termination of the internal cycle.<br />

Show cycles are always enabled in emulation mode. In master mode,<br />

show cycles are disabled coming out of reset and must be enabled by<br />

writing to the SHEN bit in the chip configuration register (CCR).<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA External Bus Interface Module (EBI) 517<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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