MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Edge Port Module (EPORT)
Memory Map and Registers
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Freescale Semiconductor, I
EPPA[7:0] — EPORT Pin Assignment Select Fields
The read/write EPPAx fields configure EPORT pins for level detection
and rising and/or falling edge detection as Table 12-2 shows.
Pins configured as level-sensitive are inverted so that a logic 0 on the
external pin represents a valid interrupt request. Level-sensitive
interrupt inputs are not latched. To guarantee that a level-sensitive
interrupt request is acknowledged, the interrupt source must keep the
signal asserted until acknowledged by software.
Pins configured as edge-triggered are latched and need not remain
asserted for interrupt generation. A pin configured for edge detection
is monitored regardless of its configuration as input or output.
EPPAx
Table 12-2. EPPAx Field Settings
00 Pin INTx level-sensitive
01 Pin INTx rising edge triggered
10 Pin INTx falling edge triggered
Pin Configuration
11 Pin INTx both falling edge and rising edge triggered
Interrupt requests generated in the EPORT module can be masked
by the interrupt controller module. EPPAR functionality is
independent of the selected pin direction.
Reset clears the EPPAx fields.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Edge Port Module (EPORT) 265
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