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MMC2107 - Freescale Semiconductor

MMC2107 - Freescale Semiconductor

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Clock Module<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

In stop mode, if the PLL is intentionally disabled, then the LOCKS bit<br />

reflects the value prior to entering stop mode. However, if FWKUP is<br />

set, then LOCKS is cleared until the PLL regains lock. Once lock is<br />

regained, the LOCKS bit reflects the value prior to entering stop<br />

mode. Furthermore, reading the LOCKS bit at the same time that the<br />

PLL loses lock does not return the current loss of lock condition.<br />

In external clock mode, LOCKS remains cleared after reset. In normal<br />

PLL mode and 1:1 PLL mode, LOCKS is set after reset.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

LOCK — PLL Lock Flag<br />

1 = PLL locked<br />

0 = PLL not locked<br />

The LOCK flag is set when the PLL is locked. PLL lock occurs when<br />

the synthesized frequency is within approximately 0.75 percent of the<br />

programmed frequency. The PLL loses lock when a frequency<br />

deviation of greater than approximately 1.5 percent occurs. Reading<br />

the LOCK flag at the same time that the PLL loses lock or acquires<br />

lock does not return the current condition of the PLL. The power-on<br />

reset circuit uses the LOCK bit as a condition for releasing reset.<br />

If operating in external clock mode, LOCK remains cleared after reset.<br />

LOCS — Sticky Loss Of Clock Flag<br />

1 = Loss of clock detected since exiting reset or oscillator not yet<br />

recovered from exit from stop mode with FWKUP = 1<br />

0 = Loss of clock not detected since exiting reset<br />

The LOCS flag is a sticky indication of whether a loss of clock<br />

condition has occurred at any time since exiting reset in normal PLL<br />

and 1:1 PLL modes. LOCS = 0 when the system clocks are operating<br />

normally. LOCS = 1 when system clocks have failed due to a<br />

reference failure or PLL failure.<br />

After entering stop mode with FWKUP set and the PLL and oscillator<br />

intentionally disabled (STPMD[1:0] = 11), the PLL exits stop mode in<br />

SCM while the oscillator starts up. During this time, LOCS is<br />

temporarily set regardless of LOCEN. It is cleared once the oscillator<br />

comes up and the PLL is attempting to lock.<br />

If a read of the LOCS flag and a loss of clock condition occur<br />

simultaneously, the flag does not reflect the current loss of clock<br />

condition.<br />

Technical Data <strong>MMC2107</strong> – Rev. 2.0<br />

232 Clock Module MOTOROLA<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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