MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
The previous situations cover normal overlap conditions that arise with
asynchronous trigger events on the two queues. An additional conflict to
consider is that the freeze condition can arise while the QADC is actively
executing CCWs. The conventional use for the debug mode is for
software/hardware debugging. When the CPU background debug mode
is enabled and a breakpoint occurs, the freeze signal is issued, which
can cause peripheral modules to stop operation. When freeze is
detected, the QADC completes the conversion in progress, unlike queue
1 suspending queue 2. After the freeze condition is removed, the QADC
continues queue execution with the next CCW in sequence.
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Freescale Semiconductor, I
Trigger events that occur during freeze are not captured. When a trigger
event is pending for queue 2 before freeze begins, that trigger event is
remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as
soon as queue 1 is finished.
Situations 12 through 19 (Figure 18-34 to Figure 18-41) show examples
of all of the freeze situations.
Q1:
T1
C1
C2
FREEZE
Figure 18-34. CCW Freeze Situation 12
FREEZE
C3
C4
CF1
T2
Q2:
C1
C2
C3
C4
Figure 18-35. CCW Freeze Situation 13
CF2
Technical Data MMC2107 – Rev. 2.0
462 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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