MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address Register Name Bit Number
Bit 7 6 5 4 3 2 1 Bit 0
0x00c6_0008
↓
0x00c6_ffff
Unimplemented
Access results in a bus monitor timeout generating an access termination transfer error.
Watchdog Timer (WDT)
Bit 15 14 13 12 11 10 9 Bit 8
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Freescale Semiconductor, I
0x00c7_0000
0x00c7_0001
0x00c7_0002
0x00c7_0003
0x00c7_0004
0x00c7_0005
Watchdog Control
Register (WCR)
See page 275.
Watchdog Modulus
Register (WMR)
See page 277.
Watchdog Count Register
(WCNTR)
See page 278.
Read: 0 0 0 0 0 0 0 0
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0
Write:
WAIT DOZE DBG EN
Reset: 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Write:
WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8
Reset: 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
Reset: 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 Bit 8
Read: WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8
Write:
Reset: 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 Bit 0
Read: WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0
Write:
Reset: 1 1 1 1 1 1 1 1
P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 18 of 34)
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA System Memory Map 71
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