MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Reset Controller Module
Functional Description
5.7.1.1 Power-On Reset
At power-up, the reset controller asserts RSTOUT. RSTOUT continues
to be asserted until V DD has reached a minimum acceptable level and,
if a PLL clock mode is selected, until the PLL achieves phase lock. Then
after approximately another 512 cycles, RSTOUT is negated and the
part begins operation.
5.7.1.2 External Reset
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5.7.1.3 Watchdog Timer Reset
5.7.1.4 Loss of Clock Reset
Asserting the external RESET pin for at least four rising CLKOUT edges
causes the external reset request to be recognized and latched. The bus
monitor is enabled and the current bus cycle is completed. The reset
controller asserts RSTOUT for approximately 512 cycles after the
RESET pin is negated and the PLL has acquired lock. The part then exits
reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the
external RESET pin during stop mode causes an external reset to be
recognized.
A watchdog timer timeout causes the watchdog timer reset request to be
recognized and latched. The bus monitor is enabled and the current bus
cycle is completed. If the RESET pin is negated and the PLL has
acquired lock, the reset controller asserts RSTOUT for approximately
512 cycles. Then the part exits reset and begins operation.
This reset condition occurs in PLL clock mode when the LOCRE bit in
SYNCR is set and either the PLL reference or the PLL fails. The reset
controller asserts RSTOUT for approximately 512 cycles after the PLL
has acquired lock. The part then exits reset and begins operation.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Reset Controller Module 137
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